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INPUT
A   B
OUTPUT
A NAND B
0 0 1
0 1 1
1 0 1
1 1 0

The NAND gate is a digital logic gate that behaves according to the truth table to the right. A LOW output results only if both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH output results.The nand gate is a universal gate in the sense that any boolean function can be implemented by nand gates.

Symbols[edit | edit source]

There are two symbols for NAND gates: the 'military' symbol and the 'rectangular' symbol. For more information see logic gate symbols.

'Military' NAND symbol

'Rectangular' NAND symbol

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Hardware description and pinout[edit | edit source]

NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs.

File:CMOS 4011 diagram.svg

This schematic diagram shows the arrangement of NAND gates within a standard 4011 CMOS integrated circuit.

CMOS version[edit | edit source]

The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates.

Availability[edit | edit source]

These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips or Texas Instruments. These are usually available in both through-hole DIL and SOIC format. Datasheets are readily available in most datasheet databases.

The standard 2-, 3-, 4- and 8-input NAND gates are available:

  • CMOS
    • 4011: Quad 2-input NAND gate
    • 4023: Triple 3-input NAND gate
    • 4012: Dual 4-input NAND gate
    • 4068: Mono 8-input NAND gate
  • TTL
    • 7400: Quad 2-input NAND gate
    • 7410: Triple 3-input NAND gate
    • 7420: Dual 4-input NAND gate
    • 7430: Mono 8-input NAND gate

Implementations[edit | edit source]

The NAND gate is the easiest to manufacture, and also has the property of functional completeness. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates. An entire processor can be created using NAND gates alone.

File:NMOS NAND.png
File:PMOS NAND.png
File:TTL npn nand.svg

TTL NAND gate

The PMOS NAND is incorrect. This schematic implements a PMOS NOR gate.

See also[edit | edit source]

External Links[edit | edit source]

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